1. Field
Disclosure provided herein relates to processing circuitry. In particular, embodiments provided herein relate to the use of memory arrays.
2. Information
Embedded processing systems typically comprise a core processing circuit which executes instructions stored in a memory. To commence execution from a reset state, the core processing circuit may initially attempt to fetch instructions for execution from an associated cache memory. If no such instructions are to be found in the cache memory, the core processing circuit may attempt to retrieve instructions from another memory through a data bus. The retrieved instructions may then be loaded to the cache memory and then fetched for execution.
While initial instructions for execution by a core processing system may be retrieved from an external memory, providing such an external memory in an embedded processing system may be costly and/or sacrifice performance in the execution of applications. Accordingly, there is a need to provide systems and methods of providing instructions to a cache memory in an embedded processing system for subsequent execution by a core processing circuit.